A phase-locked loop (PLL) circuit or system generates an output signal whose phase is related to the phase of an input signal. Conventional systems that include PLLs often include a control filter that sets the bandwidth at which the PLL circuit will follow changes in frequency of the input signal.
One drawback with using such PLLs is that the rate of change of the frequency (referred to as the slew rate) is not precisely specified. That is, the slew rate is only roughly set since the relationship between the slew rate and the bandwidth of the control filter is not linear. Another drawback with using such PLLs is that the slew rate is typically a “soft” limit and not a hard limit. As a result, even if the average slew rate over a period of time is equal to the desired slew rate over the period of time, there will typically be instants in time in which the slew rate will be higher than the desired slew rate and instants in time in which the slew rate will be lower than the desired slew rate.